Feasibility demonstration of a multi-level thin film BST capacitor technology

There is a continuing need for high density, high value (>0.1 μF) capacitors on silicon substrates for compact circuit applications. The use of alternating layers of ferroelectric and electrode thin films to construct a multi-level capacitor (MLC) structure offers the opportunity to multiply capacitance areal density with minimal increase of device thickness beyond that of the silicon substrate. Such capacitors have been demonstrated in the Pt/BST/Pt system up to 4 levels over device areas >1 mm². This paper presents experimental data, the process engineering challenges, and the methodology used to demonstrate the feasibility of the MLC technology including some aspects of process architecture, equipment, and test vehicles