A bit serial linear array DFT

A Linear array which computes the DFT in a pipelined fashion is described. The algorithm is derived from the batch processing array proposed by H.T. Kung [1] but has been modified to allow continuous operation. This computation of the DFT is a complex polynomial evaluation on the unit circle using Horner´s method having the data for the polynomial coefficients. Data and the N-th complex roots of unity are input at one end of the array and the DFT sequence is output from the other. The polynomial coefficients are stored in successive modules in the array and a new batch is latched successively with a synchronising signal. In its simplest form the design has a single system part which is replicated N times for an N-point transform. For time multiplexed modules the system throughput and hardware can be optimised for given applications. A bit serial layout for 6 micron NMOS VLSI has been designed and simulated using the FIRST silicon compiler at the University of Edinburgh.