A Register Allocation Algorithm Based on Predicate Analysis System

Author

Wang Fengqin ; Li Ying ; Zhang Zhengxia

Author_Institution

Dept. of Ordnance Sci. & Technol., Naval Aeronaut. Eng. Inst., Yantai, China

Volume

2

fYear

2009

fDate

10-11 July 2009

Firstpage

78

Lastpage

81

Abstract

In order to allocate registers efficiently for predicated code, a new algorithm based on predicate analysis system is presented, which uses binary decision diagrams for constructing refined interference graph. The algorithm is implemented in the compiler of XXX-DSP/700 chip developed by our college. Experiment results show that the number of used registers is reduced 24.51% evenly, and the average speedup of code execution time reaches 1.31.

Keywords

binary decision diagrams; optimising compilers; XXX-DSP/700 chip; binary decision diagrams; predicate analysis system; refined interference graph; register allocation algorithm; Algorithm design and analysis; Boolean functions; Data structures; Educational institutions; Information analysis; Interference; Partitioning algorithms; Performance analysis; Registers; Signal processing algorithms; Binary Decision Diagram; DSP; Predicate Analysis; Predicated Execution; Register Allocation;

fLanguage

English

Publisher

ieee

Conference_Titel

Information Engineering, 2009. ICIE '09. WASE International Conference on

Conference_Location

Taiyuan, Shanxi

Print_ISBN

978-0-7695-3679-8

Type

conf

DOI

10.1109/ICIE.2009.259

Filename

5211480