DocumentCode :
3078564
Title :
A block-diagonal structured model reduction scheme for power grid networks
Author :
Zhang, Zheng ; Hu, Xiang ; Cheng, Chung-Kuan ; Wong, Ngai
Author_Institution :
Dept. of Electr. Eng. & Comput. Sci., MIT, Cambridge, MA, USA
fYear :
2011
fDate :
14-18 March 2011
Firstpage :
1
Lastpage :
6
Abstract :
We propose a block-diagonal structured model order reduction (BDSM) scheme for fast power grid analysis. Compared with existing power grid model order reduction (MOR) methods, BDSM has several advantages. First, unlike many power grid reductions that are based on terminal reduction and thus error-prone, BDSM utilizes an exact column-by-column moment matching to provide higher numerical accuracy. Second, with similar accuracy and macromodel size, BDSM generates very sparse block-diagonal reduced-order models (ROMs) for massive-port systems at a lower cost, whereas traditional algorithms such as PRIMA produce full dense models inefficient for the subsequent simulation. Third, different from those MOR schemes based on extended Krylov subspace (EKS) technique, BDSM is input-signal independent, so the resulting ROM is reusable under different excitations. Finally, due to its blockdiagonal structure, the obtained ROM can be simulated very fast. The accuracy and efficiency of BDSM are verified by industrial power grid benchmarks.
Keywords :
circuit simulation; integrated circuit modelling; power integrated circuits; reduced order systems; BDSM scheme; EKS technique; MOR methods; PRIMA; ROM; block-diagonal structured model reduction scheme; blockdiagonal structure; column-by-column moment matching; extended Krylov subspace technique; full dense models; industrial power grid benchmarks; input-signal independent; macromodel size; massive-port systems; numerical accuracy; power grid analysis; power grid model order reduction methods; power grid networks; power grid reductions; sparse block-diagonal reduced-order models; subsequent simulation; terminal reduction; Accuracy; Computational modeling; Integrated circuit modeling; Numerical models; Power grids; Read only memory; Sparse matrices;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Design, Automation & Test in Europe Conference & Exhibition (DATE), 2011
Conference_Location :
Grenoble
ISSN :
1530-1591
Print_ISBN :
978-1-61284-208-0
Type :
conf
DOI :
10.1109/DATE.2011.5763014
Filename :
5763014
Link To Document :
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