DocumentCode
3078957
Title
Boolean function representation based on disjoint-support decompositions
Author
Bertacco, Valeria ; Damiani, Maurizio
Author_Institution
Dipartimento di Elettronica e Inf., Padova Univ., Italy
fYear
1996
fDate
7-9 Oct 1996
Firstpage
27
Lastpage
32
Abstract
The Multi-Level Decomposition Diagrams (MLDDs) of this paper are a canonical representation of Boolean functions expliciting disjoint-support decompositions. MLDDs allow the reduction of memory occupation with respect to traditional ROBDDs by decomposing logic functions recursively into simpler-and more sharable-blocks. The representation is less sensitive to variable ordering, and because of this property, analysis of the MLDD graphs allows at times the identification of better variable orderings. The identification of more terminal cases by Boolean algebra techniques makes it possible to compensate the additional-small-CPU time required to identify the disjoint-support decomposition. We expect the properties of MLDDs to be useful in several contexts, most notably logic synthesis, technology mapping, and sequential hardware verification
Keywords
Boolean functions; combinational circuits; formal verification; logic design; multivalued logic circuits; trees (mathematics); Boolean algebra techniques; Boolean function representation; canonical representation; combinational circuits; disjoint-support decompositions; logic functions; logic synthesis; memory occupation; multi-level circuits; multi-level decomposition diagrams; sequential hardware verification; technology mapping; Automata; Boolean algebra; Boolean functions; Central Processing Unit; Data structures; Hardware; Logic functions; Logic programming; Shape; Tree graphs;
fLanguage
English
Publisher
ieee
Conference_Titel
Computer Design: VLSI in Computers and Processors, 1996. ICCD '96. Proceedings., 1996 IEEE International Conference on
Conference_Location
Austin, TX
ISSN
1063-6404
Print_ISBN
0-8186-7554-3
Type
conf
DOI
10.1109/ICCD.1996.563527
Filename
563527
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