A multiseed counter TPG with performance guarantee

Author

Kagaris, Dimitrios ; Tragoudas, Spyros

Author_Institution

Dept. of Electr. Eng., Southern Illinois Univ., Carbondale, IL, USA

fYear

1996

fDate

7-9 Oct 1996

Firstpage

34

Lastpage

39

Abstract

Several mechanisms based on ROMs, LFSRs, counters, cellular automata, have been proposed as built-in test pattern generators with trade-offs between hardware and time overhead. This paper presents and analyses a scheme based on a counter with multiple seeds to generate a test set with low hardware overhead. A fast CAD tool determines the number of clock cycles required for the test set generation and this number is shown to be close to the best possible. A comparison to other existing approaches on the ISCAS´85 benchmarks shows that the proposed mechanism can offer a favorable hardware/time overhead for many circuits

Keywords

automatic test software; built-in self test; logic CAD; logic testing; ISCAS´85 benchmarks; built-in test pattern generators; fast CAD tool; hardware/time overhead; low hardware overhead; multiseed counter test pattern generator; performance guarantee; test set generation; Clocks; Counting circuits; Genetic mutations; Hardware; Merging; NP-hard problem; Testing;

fLanguage

English

Publisher

ieee

Conference_Titel

Computer Design: VLSI in Computers and Processors, 1996. ICCD '96. Proceedings., 1996 IEEE International Conference on

Conference_Location

Austin, TX

ISSN

1063-6404

Print_ISBN

0-8186-7554-3

Type

conf

DOI

10.1109/ICCD.1996.563528

Filename

563528