Low-power MPEG-4 video encoder design

The improving resolutions of new video appliances continuously increase the throughput requirements of video codecs and complicate the challenges encountered during their cost-efficient design. The energy limitations of mobile appliances create the demand for low-power implementations. We propose a custom high-performance MPEG-4 video encoder. The fully dedicated video pipeline is realized using a systematic design approach and exploits the inherent functional parallelism of the compression algorithm. Memory optimizations and algorithmic optimizations combined at the high-level and their effect on the power-efficiency is demonstrated. The resulting MPEG-4 video encoder contains a tailored memory hierarchy; uses burst oriented accesses to external memory and supports real-time processing of 30 4CIF frames per second while only consuming 71 mW in a 180 nm, 1.62 V UMC technology.