DocumentCode :
3079221
Title :
Comparison and analysis of various PFD architecture for a phase locked loop design
Author :
AnushKannan, N.K. ; Mangalam, H. ; Dharani, V. Anoor ; Divya, G. ; Esack, N. ; Gokulraj, M.
Author_Institution :
Anna Univ., Chennai, India
fYear :
2013
fDate :
26-28 Dec. 2013
Firstpage :
1
Lastpage :
4
Abstract :
Phase Frequency Detector (PFD) plays a crucial role and an essential part in Phase Locked Loop (PLL). PFD has an advantageous function over the Phase Detector (PD) and Frequency Detector (FD) by detecting phase and frequency detection at a time. PFD compares the phase difference between the input reference signal and the output signal from voltage controlled oscillator (VCO). Generation of Up and Down clock signals depend upon phase and frequency deviation. The key factor is to observe the dead zone problem in various PFD structures. This Paper presents the Comparison and Analysis of different PFD architectures, designed and simulated using T-Spice in 130nm technology.
Keywords :
clocks; phase detectors; phase locked loops; voltage-controlled oscillators; PFD; PLL; T-Spice; VCO; clock signals; dead zone problem; phase frequency detector; phase locked loop; reference signal; size 130 nm; voltage controlled oscillator; Charge pumps; Delays; Logic gates; Phase frequency detector; Phase locked loops; Transistors; Voltage-controlled oscillators; Dead zone; PFD; PLL;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Computational Intelligence and Computing Research (ICCIC), 2013 IEEE International Conference on
Conference_Location :
Enathi
Print_ISBN :
978-1-4799-1594-1
Type :
conf
DOI :
10.1109/ICCIC.2013.6724238
Filename :
6724238
Link To Document :
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