DocumentCode
3079623
Title
Multiplexor network generation in high level synthesis
Author
Fang, Yung-Ming ; Wong, D.E.
Author_Institution
Dept. of Electr. & Comput. Eng., Texas Univ., Austin, TX, USA
fYear
1996
fDate
7-9 Oct 1996
Firstpage
78
Lastpage
83
Abstract
In high level synthesis, after the binding stage, multiplexor network is generated to connect the outputs of modules (functional-units/registers) to the inputs of modules. In this paper we present an algorithm to generate a 2-to-1 multiplexor network with minimum number of multiplexors. Our algorithm is based on iteratively solving minimum vertex cover problems. Experimental results show that our approach obtains 8 to 25% improvement over a direct multiplexor-forest approach
Keywords
circuit CAD; high level synthesis; multiplexing equipment; 2-to-1 multiplexor network; high level synthesis; minimum vertex cover problems; multiplexor network; multiplexor network generation; High level synthesis; Inspection; Intelligent networks; Merging; Multiplexing;
fLanguage
English
Publisher
ieee
Conference_Titel
Computer Design: VLSI in Computers and Processors, 1996. ICCD '96. Proceedings., 1996 IEEE International Conference on
Conference_Location
Austin, TX
ISSN
1063-6404
Print_ISBN
0-8186-7554-3
Type
conf
DOI
10.1109/ICCD.1996.563537
Filename
563537
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