DocumentCode
3079795
Title
Hierarchical vector clock: scalable plausible clock for detecting causality in large distributed systems
Author
Khotimsky, Denis A. ; Zhuklinets, Igor A.
Author_Institution
AT&T Bell Labs., Holmdel, NJ, USA
fYear
1999
fDate
1999
Firstpage
156
Lastpage
163
Abstract
Modern ATM networks possess a multilevel hierarchical structure, where certain sets of physical or logical nodes are grouped together according to physical, geographical, and/or administrative consideration. A distributed application running on top of such network may contain thousands of sites belonging to different logical nodes with the transport channels between them extending through multiple domain boundaries and crossing multiple hierarchical levels. While knowledge of causality between the events in such a system is essential for analyzing the system behavior and ensuring the correct operation through solving various problems related to mutual exclusion, consistency maintenance, fault tolerance and recovery, etc., the accurate tracking of the causality information may be infeasible due to the system´s size and lifespan. For example, the communication and storage overhead involved in using the conventional vector clock, which allows causality to be completely characterized, is linear in the number of sites of a distributed system. In this paper we propose a new logical time system, called hierarchical vector clock or HVC, which allows causality to be detected between events in a large distributed system with a high degree of accuracy, while being ideally suited for the hierarchical structure of an underlying network and able to scale gracefully with the increasing number of distributed sites
Keywords
asynchronous transfer mode; causality; clocks; distributed processing; time measurement; HVC; causality; causality detection; consistency maintenance; distributed application; distributed sites; fault recovery; fault tolerance; hierarchical vector clock; large distributed systems; logical nodes; logical time system; modern ATM networks; multilevel hierarchical structure; multiple domain boundaries; mutual exclusion; scalable plausible clock; underlying network; Clocks; Communication networks; Event detection; Fault tolerant systems; Information analysis; Intelligent networks; Vectors;
fLanguage
English
Publisher
ieee
Conference_Titel
ATM, 1999. ICATM '99. 1999 2nd International Conference on
Conference_Location
Colmar
Print_ISBN
0-7803-5428-1
Type
conf
DOI
10.1109/ICATM.1999.786798
Filename
786798
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