Developing an integrated verification and debug methodology

As design complexity of LSI systems increase, so does the verification challenges. It is very important, yet difficult to find all design errors and correct them in a timely manner. This paper presents our experience with a new verification and debug methodology based on the combination of formal verification and automated debugging. This methodology, which is applied to the development of a DDR2 memory design targeted for an FGPA, is found to significantly reduce the verification and debug tasks typically performed.