Implementation of LFSR on ASIC

The intension of this work is to design ASIC (Application Specific Integrated Circuit) for LFSRs (Linear feedback shift register) used in cryptography systems.(Stream ciphering). Presently FPGAs (Field Programmable Gate Array) and Processors are used for this purpose which have speed limitations. Since FPGAs have general structure and implementing LFSRs in FPGAs are unable to achieve the required speed. So ASIC based programmable LFSRs are required to the requirements of speed which are used in stream ciphering. Implementation of any design on ASIC is only possible with EDA (Electronic Design automation) tools. In this paper the cadence tool is used to accomplish the task. LFSRs are designed using Verilog and the maximum frequency is achieved and determined the critical path delay. The design is verified both in functional and timing simulation. Its performance is far higher than traditional FPGAs in terms of Speed.