DocumentCode
3080128
Title
A feasible scheduling algorithm for per-VC queueing ATM switches
Author
Zhou, Peifang ; Yang, Oliver W W
Author_Institution
Sch. of Inf. Technol. & Eng., Ottawa Univ., Ont., Canada
fYear
1999
fDate
1999
Firstpage
295
Lastpage
304
Abstract
This paper introduces a scheduling algorithm for per-VC queueing ATM switches. Our proposed per-VC queueing scheduler (PVQS) achieves a low maximum delay, provides bandwidth guarantee, and fairly allocates excess capacity. The computation in PVQS is carried out on a per-connection basis, not on a per-cell basis which is mandatory in the virtual time-stamp type of approach. This leads to a significant reduction in computational effort and makes PVQS a feasible candidate for practical implementation in per-VC queueing ATM switches
Keywords
asynchronous transfer mode; delays; queueing theory; scheduling; telecommunication traffic; ATM switches; bandwidth guarantee; delay; fair capacity allocation; per-VC queueing scheduler; virtual time-stamp; Asynchronous transfer mode; Clocks; Information technology; Processor scheduling; Quality of service; Scheduling algorithm; Switches; Tellurium; Traffic control; Virtual colonoscopy;
fLanguage
English
Publisher
ieee
Conference_Titel
ATM, 1999. ICATM '99. 1999 2nd International Conference on
Conference_Location
Colmar
Print_ISBN
0-7803-5428-1
Type
conf
DOI
10.1109/ICATM.1999.786815
Filename
786815
Link To Document