Digital neural cell scheduler for ATM switching

An input buffer-type ATM switch with a window-based contention algorithm is proposed, modeled in VHDL, for a high-speed cell scheduler for ATM switching. A digital Hopfield neural cell scheduler which has the ability of real-time processing is used to solve loss of throughput due to head-of-line (HOL) and internal blocking when FIFO queueing is employed at the banyan network. In this scheduler, consequently, a tag value which has a destination-cell address is changed into a corresponding binary pattern, modified into a non-internal blocking pattern by preprocessing and optimization, which results in the reduction of the work load of the cell scheduler and smoothing of the priority control of the scheduler. By skipping random input operations and reducing the demand on arithmetic operations by operating on a minimized number of bits in this scheduler, it is found that we can minimize the delay for scheduling and maximise the selection of non-blocking cells leading to high performance. We use a performance metrix, evaluating its performance in an average number of clock cycles needed for scheduling a cell from the queue to the banyan network