0.5 V 320 MHz 8 b multiplexer/demultiplexer chips based on a gate array with regular-structured DTMOS/SOI

Thin film SOI-CMOS transistors are promising for high-speed low-power multiplexer and demultiplexer applications because they feature low parasitic capacitances and flexible bias-control of the body region under the channel. Direct connection of the gate and the associated body in SOI transistors enhances circuit speed at ultra-low voltage, as verified at the integration level of ALUs. Applied to gate arrays, this would greatly ease design and technology migration to ultra-low voltage, and improve turn-around time and productivity of high-speed low-power devices. The 8 b multiplexer and the 8 b demultiplexer based on a 0.32 /spl mu/m gate array technology with regular-structured dynamic-threshold voltage CMOS/SOI use flip-flop circuits that exploit high-speed and low-power SOI structures. At 0.5 V, the multiplexer operates at 320 MHz with 2.0 mW, and the demultiplexer operates at 380 Mz with 1.4 mW.