Title :
FPGA implementation for channel estimations based on Wiener LMS for DS-CDMA
Author :
Elnamaky, Mohamed ; Ahmed-Ouameur, Messaoud ; Massicotte, Daniel
Author_Institution :
Dept. of Electr. & Comput. Eng., Quebec Univ., Trois-Rivieres, Que., Canada
Abstract :
The estimation of channel delays along with their respective complex channel coefficients of different users constitutes the first stage in the detection process at the receiving base station in a DS-CDMA communication system. A multiuser steepest Wiener LMS (MS-WLMS) like structure algorithm along with smoothing/prediction filters to improve tracking quality is suggested. This paper presents a customized and fixed-point hardware parallel implementation of the proposed algorithm for WCDMA uplink transmission in third generation (3G) wireless system. Additional speedup in the execution time is achieved over the well known maximum likelihood channel estimation for DS-CDMA. It is also shown that our solution could achieve the real-time requirements of 3GPP standards applied in WCDMA systems.
Keywords :
3G mobile communication; broadband networks; channel estimation; code division multiple access; field programmable gate arrays; least mean squares methods; maximum likelihood estimation; spread spectrum communication; stochastic processes; 3G wireless system; 3GPP standards; DS-CDMA; FPGA; WCDMA uplink transmission; base station; channel coefficients; channel delays; fixed-point hardware parallel implementation; maximum likelihood channel estimation; multiuser steepest Wiener LMS; prediction filters; smoothing filters; third generation wireless system; tracking quality; Base stations; Channel estimation; Delay estimation; Field programmable gate arrays; Filters; Hardware; Least squares approximation; Maximum likelihood detection; Multiaccess communication; Smoothing methods;
Conference_Titel :
Signal Processing Systems Design and Implementation, 2005. IEEE Workshop on
Print_ISBN :
0-7803-9333-3
DOI :
10.1109/SIPS.2005.1579940
