Non-volatility for Ultra-Low Power Asynchronous Circuits in Hybrid CMOS/Magnetic Technology

This paper addresses the power reduction techniques for the ultra-low power integrated circuits. We propose to implement non-volatile asynchronous circuits which will have a quasi-zero leakage consumption, almost instant back-up and wake-up time and will be robust to unstable supply environments. This paper presents the implementation of the non-volatile C-element and Half-Buffer, based on hybrid technology incorporating 28nm CMOS FD-SOI and 40nm STT-MRAM magnetic technologies. We discuss our recent simulation results of the proposed non-volatile blocks and as well more complex structures based on them. We derive the criteria of the implementation efficiency and compare the conventional asynchronous blocks with the proposed non-volatile ones.