A Cluster Timing Algorithm for drift chambers readout electronics

A Cluster Timing Algorithm has been developed in order to store information coming from a 6 bits, 1 Gsample/s flash ADC. In particular the algorithm detects signal peaks and stores their amplitude and timing information. A Xilinx ML605 Evaluation Board, making use of a FPGA Virtex 6 core, has been employed in order to develop and test the VHDL code. The final goal is to develop a VME board capable of reading up to, at least, 4 ADC channels. The current algorithm, under continuous improvement, applied to simulated signals, satisfies the efficiency and timing constraints imposed. Code optimizations are currently under development.