Title :
A CAM-based VLSI architecture for shared buffer ATM switch with fuzzy controlled buffer management
Author :
Dou, Chie ; Shieh, Ming-Der
Author_Institution :
Nat. Yunlin Inst. of Technol., Taiwan
Abstract :
This paper proposes a CAM-based shared buffer ATM switch-on-a-chip architecture that takes network-element internal congestion control into consideration. This internal congestion control includes selective cell discard, priority service scheduling, and fuzzy controlled buffer management. To provide “fair” access to the network resources for all users, the SMXQ buffer control scheme is adopted. The SMXQ scheme assumes a queue length threshold is chosen for the logical queue pertaining to each output port, and if the queue length exceeds the threshold the arriving cells are discarded. Selective cell discard is performed per port basis when the shared buffer is full or the queue length of a particular output port exceeds its threshold. For each output port, {CLP=1} cells will be discarded before any {CLP=0} cell is discarded. The set of chosen queue length thresholds are computed directly by an on-chip fuzzy congestion controller (FCC) in sub microsecond intervals
Keywords :
VLSI; asynchronous transfer mode; fuzzy control; queueing theory; switching circuits; telecommunication congestion control; buffer control; buffer management; fuzzy congestion controller; fuzzy control; internal congestion control; priority service scheduling; queue length thresholds; selective cell discard; shared buffer ATM switch; Asynchronous transfer mode; Communication system traffic control; Computer architecture; Engineering management; Fuzzy control; Quality of service; Switches; Technology management; Traffic control; Very large scale integration;
Conference_Titel :
Computer Design: VLSI in Computers and Processors, 1996. ICCD '96. Proceedings., 1996 IEEE International Conference on
Conference_Location :
Austin, TX
Print_ISBN :
0-8186-7554-3
DOI :
10.1109/ICCD.1996.563551