Title :
A sub-1 V triple-threshold CMOS/SIMOX circuit for active power reduction
Author :
Fujii, K. ; Douseki, T. ; Harada, M.
Author_Institution :
NTT Syst. Electron. Labs., Kanagawa, Japan
Abstract :
The triple-Vth CMOS/SIMOX circuit presented uses 0.25 /spl mu/m SIMOX devices with a small subthreshold swing to reduce leakage current in both the active and standby modes without speed degradation. A 16 b carry-lookahead adder uses the triple-Vth scheme. The logic gates in the critical carry-paths use low-Vth MOSFETs and other logic gates in non-critical paths are composed of medium-Vth MOSFETs. The ratio of the low-Vth MOSFET count to the medium-Vth MOSFET count is 1.3:1.0. Performance is compared with that of an all low-Vth adder using simulation. The delay times at 0.5 V are 5.2 ns for triple-Vth and 4.5 ns for all low-Vth. The active leakage power dissipations at 0.5 V are 38 /spl mu/W and 60 /spl mu/W respectively.
Keywords :
CMOS logic circuits; 0.25 micron; 0.5 V; 16 bit; 38 muW; 4.5 ns; 5.2 ns; 60 muW; MOSFET; active power dissipation; carry-lookahead adder; delay time; leakage current; logic gate; simulation; subthreshold swing; triple-threshold CMOS/SIMOX circuit; Adders; CMOS logic circuits; CMOS technology; Delay effects; Leakage current; Logic devices; Logic gates; MOSFETs; Power dissipation; Rails;
Conference_Titel :
Solid-State Circuits Conference, 1998. Digest of Technical Papers. 1998 IEEE International
Conference_Location :
San Francisco, CA, USA
Print_ISBN :
0-7803-4344-1
DOI :
10.1109/ISSCC.1998.672430
