Title :
Development of hardware in loop for simulation accerlation
Author :
Gurav, Snehalata S. ; Sumitra Devi, K.
Author_Institution :
Dayananda Sagar Inst. ofTechnology, Bangalore, India
Abstract :
The speed of the HDL simulator is the primary bottleneck of the design cycle when it comes to verification. Limiting the number of simulation tests because there is not enough time is alarming and raises doubt about the completeness of verification. Even after doing such verification on the simulation model/RTL (behavioral) there is no hardware proof. After synthesis we will have to repeat the verification process once again. This consumes some more time.
Keywords :
field programmable gate arrays; hardware description languages; logic testing; RTL model; behavioral model; hardware in loop for simulation acceleration; simulation model; verification process; Field programmable gate arrays; Hardware; Hardware design languages; Integrated circuit modeling; Logic gates; Microprocessors; Program processors;
Conference_Titel :
India Conference (INDICON), 2012 Annual IEEE
Conference_Location :
Kochi
Print_ISBN :
978-1-4673-2270-6
DOI :
10.1109/INDCON.2012.6420651
