DocumentCode :
3080508
Title :
ReliNoC: A reliable network for priority-based on-chip communication
Author :
Kakoee, Mohammad Reza ; Bertacco, Valeria ; Benini, Luca
Author_Institution :
DEIS, Univ. of Bologna, Bologna, Italy
fYear :
2011
fDate :
14-18 March 2011
Firstpage :
1
Lastpage :
6
Abstract :
The reliability of networks-on-chip (NoC) is threatened by low yield and device wearout in aggressively scaled technology nodes. We propose ReliNoC, a network-on-chip architecture which can withstand failures, while maintaining not only basic connectivity, but also quality-of-service support based on packet priorities. Our network leverages a dual physical channel switch architecture which removes the control overhead of virtual channels (VCs) and utilizes the inherent redundancy within the 2-channel switch to provide spares for faulty elements. Experimental results show that ReliNoC provides 1.5 to 3 times better network physical connectivity in presence of several faults, and reduces the latency of both high and low priority traffic by 30 to 50%, compared to a traditional VC architecture. Moreover, it can tolerate up to 50 faults within an 8×8 mesh at only 10 and 40% latency overhead on control and data packets for PARSEC traces. Synthesis results show that our reliable architecture incurs only 13% area overhead on the baseline 2-channel switch.
Keywords :
network-on-chip; quality of service; telecommunication network reliability; PARSEC traces; ReliNoC; networks-on-chip; priority-based on-chip communication; quality-of-service; reliable network; virtual channels; Fault tolerance; Fault tolerant systems; Quality of service; Registers; Routing; Switches;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Design, Automation & Test in Europe Conference & Exhibition (DATE), 2011
Conference_Location :
Grenoble
ISSN :
1530-1591
Print_ISBN :
978-1-61284-208-0
Type :
conf
DOI :
10.1109/DATE.2011.5763112
Filename :
5763112
Link To Document :
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