Title :
NBTI resistant SRAM design
Author :
Ahmed, Fahad ; Milor, Linda
Author_Institution :
Sch. of Electr. & Comput. Eng., Georgia Inst. of Technol., Atlanta, GA, USA
Abstract :
Increasing operating temperatures and electrical fields, combined with the scaling of dimensions, have contributed to faster device aging due to negative bias temperature instability (NBTI). This problem is further compounded in SRAM cells because SRAMs use devices that are among the smallest for a technology node. Since device degradation is a gradual process, it is proposed that if the threshold voltage increase in PMOS devices of SRAM cells can be monitored, failing cells in SRAMs can be detected and the SRAM can be operated without failures, given available memory redundancy. Using an experimentally verified NBTI model, we study the performances of conventional 6T SRAM cells, as a function of NBTI degradation, in the presence of process variations. An on-chip monitoring scheme is presented that can be embedded within conventional SRAM designs without affecting normal device operation. It identifies cells susceptible to read and write failures in the near future, enabling the prediction of cell failure before its occurrence in order to trigger reconfiguration.
Keywords :
MOS integrated circuits; SRAM chips; failure analysis; fault diagnosis; integrated circuit reliability; NBTI; PMOS device; SRAM cell design; negative bias temperature instability; on-chip monitoring scheme; Arrays; Degradation; MOS devices; Monitoring; Noise; Random access memory; Stress; NBTI monitoring; SRAM cell; cache; fault prediction; reliability; stability analysis;
Conference_Titel :
Advances in Sensors and Interfaces (IWASI), 2011 4th IEEE International Workshop on
Conference_Location :
Savelletri di Fasano
Print_ISBN :
978-1-4577-0623-3
Electronic_ISBN :
978-1-4577-0622-6
DOI :
10.1109/IWASI.2011.6004692