Design of FPGA based 8-bit RISC controller IP core using VHDL

This paper describes the design, development and implementation of an 8-bit RISC controller IP core. The controller has been designed using Very high speed integrated circuit Hardware Description Language (VHDL). The design constraints are speed, power and area. This controller is efficient for specific applications and suitable for small applications. This non-pipelined controller has four units: - Fetch, Decode, Execute and a stage control unit. It has an in built program and data memory. Also it has four ports for communicating with other I/O devices. A hierarchical approach has been used so that basic units can be modeled using behavioral programming. The basic units are combined using structural programming. The design has been implemented using ALTERA STRATIX II FPGA.