DocumentCode :
3080979
Title :
Multiple-valued duplex asynchronous data transfer scheme for interleaving in LDPC decoders
Author :
Onizawa, Naoya ; Mochizuki, Akira ; Hanyu, Takahiro ; Gaudet, Vincent C.
Author_Institution :
Res. Inst. of Electr. Commun., Tohoku Univ., Sendai, Japan
fYear :
2005
fDate :
19-21 May 2005
Firstpage :
138
Lastpage :
143
Abstract :
A novel duplex asynchronous data-transfer scheme based on multiple-valued encoding is proposed for interleaving in low-density parity-check (LDPC) decoders, where high-throughput interleavers between variable and check nodes without clock-distribution problems are highly advantageous. Since control signals and data from mutual nodes are multiplexed using a multi-level dual-rail codeword, the number of communication steps can be greatly reduced, which results in high-speed communication without any additional wires. The hardware is simply implemented by utilizing a multiple-valued current-mode circuit because all the information can be superposed on the same line. The advantages of the proposed asynchronous data-transfer scheme are discussed in comparison with corresponding synchronous and conventional asynchronous schemes.
Keywords :
asynchronous circuits; encoding; multivalued logic circuits; parity check codes; LDPC decoders; clock-distribution problem; dual rail codeword; low-density parity-check; multilevel codeword; multiple valued current-mode circuit; multiple valued duplex asynchronous data transfer scheme; multiple valued encoding; Clocks; Communication system control; Electronic mail; Hardware; Interleaved codes; Iterative algorithms; Iterative decoding; Parity check codes; Throughput; Wires;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Multiple-Valued Logic, 2005. Proceedings. 35th International Symposium on
ISSN :
0195-623X
Print_ISBN :
0-7695-2336-6
Type :
conf
DOI :
10.1109/ISMVL.2005.29
Filename :
1423175
Link To Document :
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