Energy-aware dual-rail bit-wise completion pipelined multipliers design

Energy-awareness indicates the scalability of the system energy with changing conditions and quality requirements. Because of the encoding format and operation sequence, dual-rail encoding circuits are not naturally energy aware to the changing of input precision. A novel technique, zero insertion, to design energy-aware arithmetic circuits in dual-rail encoding logic is developed. By using s to replace the redundant data 0s in high order bits, the designed circuits have significant energy savings as well as latency reduction under different input precision probability while maintaining speed-independency. A group of parallel multipliers have been designed and simulated to demonstrate the effectiveness of this technique. The overhead and additional costs in control signal generation circuit are also discussed.