Design and synthesis of Wishbone bus Dataflow interface architecture for SoC integration

The field of Electronics and Communication Applications, especially the VLSI design, has witnessed tremendous changes on account of research and development in SoC (System-on-Chip) technology during the last four decades. The introduction and advancement of multimillion-gate chips technology with new levels of integration has been mainly responsible for these revolutionary changes. It is predicted that by the end of 2015 System-on-Chips (SoCs), using 25-nm will grow to 17 billion transistors running at 30GHz. In the modern scenario of IP reuse, the compatibility of the IP cores has become a challenging task as the cores available for reuse and designed earlier, are usually designed with different criteria, and may be having inconsistency between their input/output port specifications. This paper endeavors to address the above problems and challenges in the SoC bus architecture with special reference to Wishbone bus architecture especially Wishbone bus interface. A SoC which utilizes ALU master cores and memory slave cores using Wishbone Dataflow bus interconnection scheme has been designed for this purpose. The final implementations have been done in XILINX FPGA platform. The synthesis of the system is done using Xilinx 12.3 ISE and simulation results archived by using ISim Simulator. The results prove that with Dataflow interface architecture a low cost, portable and Time to market SoC having features like Less Area and High Speed can be designed successfully.