Fast transient analysis of 3-D stacked on-chip power distribution network with power/ground through silicon vias by using block latency insertion method

Author

Nagata, Daisei ; Sekine, Taku ; Asai, Hiroki

Author_Institution

Dept. of Mech. Eng., Shizuoka Univ., Hamamatsu, Japan

fYear

2013

fDate

12-15 Dec. 2013

Firstpage

64

Lastpage

67

Abstract

In this paper, we apply the block latency insertion method (block-LIM) to the transient analysis of on-chip power distribution networks (PDNs) with power/ground through silicon vias (P/G TSVs). The block-LIM is suitable for simulations of circuits including a lot of coupling elements such as a mutual inductance and mutual capacitance. Numerical results show that the block-LIM can reduce the computational cost compared with HSPICE in the simulation of the equivalent circuit of the on-chip PDN with the P/G TSVs.

Keywords

circuit simulation; equivalent circuits; integrated circuit modelling; three-dimensional integrated circuits; transient analysis; 3D stacked on-chip power distribution network; HSPICE; block latency insertion method; block-LIM; circuit simulation; equivalent circuit; fast transient analysis; mutual capacitance; mutual inductance; power-ground through silicon vias; Equivalent circuits; Integrated circuit modeling; Silicon; Solid modeling; System-on-chip; Through-silicon vias; Topology; block latency insertion method (block-LIM); latency insertion method (LIM); power/ground through silicon via (P/G TSV); three-dimensional stacked on-chip power distribution network (PDN);

fLanguage

English

Publisher

ieee

Conference_Titel

Electrical Design of Advanced Packaging and Systems Symposium (EDAPS), 2013 IEEE

Conference_Location

Nara

Print_ISBN

978-1-4799-2313-7

Type

conf

DOI

10.1109/EDAPS.2013.6724390

Filename

6724390