Title :
Low power high speed FIR filter design using Null Convention Logic
Author :
Malathi, D. ; Madheswaran, M.
Author_Institution :
Dept. of ECE, Kongu Eng. Coll., Perundurai, India
Abstract :
An asynchronous delay insensitive Null Convention Logic (NCL) with dual rail signal has been used to design an improved low power high speed FIR filter and presented in this paper. NCL reduces the dynamic power consumption by reducing the switching activity. The power delay product of FIR filter using both conventional and NCL CMOS model has been estimated and compared in 90 nm technology with a frequency of 250MHz at 1.2V. Power reduction of 22% is achieved for the supply voltage of 2.5V in NCL CMOs model compared to conventional CMOS model.
Keywords :
CMOS logic circuits; FIR filters; asynchronous circuits; integrated circuit modelling; logic design; low-power electronics; NCL CMOS model; asynchronous delay insensitive NCL; dual-rail signal; dynamic power consumption; frequency 250 MHz; low-power high-speed FIR filter design; null-convention logic; power delay product; power reduction; size 90 nm; switching activity; voltage 1.2 V; voltage 2.5 V; Adders; CMOS integrated circuits; Equations; Finite impulse response filter; Logic gates; Power dissipation; Semiconductor device modeling;
Conference_Titel :
India Conference (INDICON), 2012 Annual IEEE
Conference_Location :
Kochi
Print_ISBN :
978-1-4673-2270-6
DOI :
10.1109/INDCON.2012.6420741
