Correlation of PDN impedance between measurements and simulation of 3D-SiP

Author

Kawaguchi, Shogo ; Sato, Mitsuhisa ; Takatani, Hiroki ; Tanaka, Yuichi ; Fujita, Hideaki ; Suto, Yoichi ; Sudo, Toshio

Author_Institution

Shibaura-Inst. of Technol., Tokyo, Japan

fYear

2013

fDate

12-15 Dec. 2013

Firstpage

158

Lastpage

161

Abstract

Recently, ultra-wide bus 3D-SiP with TSV´s has attracted great attention to achieve energy-saving and high-performance system level module. TSV technology is a new technology of vertical wiring to make shorter than the conventional wire bonding. However, the power supply integrity and signal integrity has become an issue due to the increase of simultaneous switching output buffers. In this paper, PDN impedances of 3D-SiP were examined by the measurement and simulation. Simulated PDN impedances of three chips were well correlated with the measured results.

Keywords

integrated circuit interconnections; integrated circuit measurement; system-in-package; three-dimensional integrated circuits; wiring; 3D-SiP measurement; 3D-SiP simulation; PDN impedance correlation; TSV technology; energy-saving; high-performance system level module; power distribution network; power supply integrity; signal integrity; simultaneous switching output buffers; ultrawide bus 3D-SiP; vertical wiring technology; wire bonding; Capacitance; Impedance; Impedance measurement; Noise; Semiconductor device measurement; Silicon; Through-silicon vias; 3D-SiP; measurement; on-die capacitance; power distribution network (PDN); simultaneous switching noise; ultra-wide bus;

fLanguage

English

Publisher

ieee

Conference_Titel

Electrical Design of Advanced Packaging and Systems Symposium (EDAPS), 2013 IEEE

Conference_Location

Nara

Print_ISBN

978-1-4799-2313-7

Type

conf

DOI

10.1109/EDAPS.2013.6724413

Filename

6724413