Title :
Signal integrity design of via with extra routing stub for device routing flexibility
Author :
Lopez Miralrio, Enrique ; Mendez Ruiz, Cesar ; Lin, Tao ; Sytwu, James ; Hsu, John ; Su, Tao ; Chunfei Ye ; Xiaoning Ye
Author_Institution :
Datacenter & Connected Syst. Group, Intel Corp., Tlaquepaque, Mexico
Abstract :
Computer systems today show a trend toward higher data rate, smaller form factor and flexible routing option to accommodate different configurations. This paper presents signal integrity impact study of having a routing stub on via in order to have a choice of which device to use. Via with routing stub is modeled using 3-D field solver. Signal integrity analysis is performed for PCIE Gen3 (8Gbps) and SATA3 (6Gbps) to demonstrate the margin loss due to various routing stub lengths. For the simulated topology, results show that for routing stub longer than 100mils, there is significant margin loss, which may even result in no solution space for PCIE Gen3 and SATA3. For routing stub less than 50mils, there is a few inches of solution space reduction equivalently according to the data rate.
Keywords :
network routing; printed circuit interconnections; vias; 3D field solver; PCB; PCIE Gen3; SATA3; bit rate 6 Gbit/s; bit rate 8 Gbit/s; computer systems; data rate; device routing flexibility; extra routing stub; margin loss; routing stub lengths; small form factor; solution space reduction; via signal integrity design; Benchmark testing; Insertion loss; Resonant frequency; Routing; Silicon; Three-dimensional displays; Topology; PCI Express; SATA; high frequency modeling; routing stub; signal integrity;
Conference_Titel :
Electrical Design of Advanced Packaging and Systems Symposium (EDAPS), 2013 IEEE
Conference_Location :
Nara
Print_ISBN :
978-1-4799-2313-7
DOI :
10.1109/EDAPS.2013.6724421
