• DocumentCode
    3082931
  • Title

    Power optimization in heterogenous datapaths

  • Author

    Del Barrio, Alberto A. ; Memik, Seda Ogrenci ; Molina, Maria C. ; Mendias, Jose M. ; Hermida, Roman

  • Author_Institution
    Archit. & Technol. of Comput. Syst., Univ. Complutense de Madrid (UCM), Madrid, Spain
  • fYear
    2011
  • fDate
    14-18 March 2011
  • Firstpage
    1
  • Lastpage
    6
  • Abstract
    Heterogenous datapaths maximize the utilization of functional units (FUs) by customizing their widths individually through fragmentation of wide operands. In comparison, slices in large functional units in a homogenous datapath could be spending many cycles not performing actual useful work. Various fragmentation techniques demonstrated benefits in minimizing the total functional unit area. Upon a closer look at fragmentation techniques, we observe that the area savings achieved by heterogenous datapaths can be traded-off for power optimization. Our specific approach is to introduce choices for functional units with power/area trade-offs for different fragmentation and allocation choices, for reducing power consumption while satisfying the area constraint imposed on the heterogenous datapath. As low power FUs in literature produce an area penalty, a methodology must be developed in order to introduce them in the HLS flow while complying with the area constraint. We propose an allocation and module selection algorithms that pursue a trade-off between area and power consumption for fragmented datapaths under a total area constraint. Results show that it is possible to reduce power by 37% on average (49% in the best case). Moreover latency and cycle time will be equal or nearly the same as in the baseline case, which will lead to an energy reduction, too.
  • Keywords
    high level synthesis; power aware computing; HLS flow; allocation selection algorithm; area trade-off; energy reduction; fragmentation techniques; functional unit area; heterogenous datapath; high-level synthesis technique; module selection algorithm; power consumption; power optimization; power trade-off; Adders; Discrete cosine transforms; Optimization; Power demand; Resource management; Scheduling; Switches; HLS; area; low-power;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Design, Automation & Test in Europe Conference & Exhibition (DATE), 2011
  • Conference_Location
    Grenoble
  • ISSN
    1530-1591
  • Print_ISBN
    978-1-61284-208-0
  • Type

    conf

  • DOI
    10.1109/DATE.2011.5763226
  • Filename
    5763226