DocumentCode
3082939
Title
Fault location based on circuit partitioning
Author
Pomeranz, Irith ; Reddy, Sudhakar M.
Author_Institution
Dept. of Electr. & Comput. Eng., Iowa Univ., Iowa City, IA, USA
fYear
1996
fDate
7-9 Oct 1996
Firstpage
242
Lastpage
247
Abstract
We propose a method of fault diagnosis that reduces the number of simulations required to locate defect site(s) by logically partitioning the circuit into subcircuits. Candidate subcircuits that potentially contain the defect site(s) are identified and further partitioned, until the defect site is located with the required resolution. Experimental results are presented to demonstrate the effectiveness of circuit partitioning in reducing the number of fault simulations
Keywords
fault diagnosis; integrated circuit testing; logic partitioning; logic testing; circuit partitioning; circuit-under-test; fault diagnosis; fault location; fault simulations; faulty behavior; single line stuck-at faults; subcircuits; Circuit faults; Circuit simulation; Cities and towns; Computational modeling; Computer simulation; Error correction; Fault diagnosis; Fault location; Sequential circuits; Testing;
fLanguage
English
Publisher
ieee
Conference_Titel
Computer Design: VLSI in Computers and Processors, 1996. ICCD '96. Proceedings., 1996 IEEE International Conference on
Conference_Location
Austin, TX
ISSN
1063-6404
Print_ISBN
0-8186-7554-3
Type
conf
DOI
10.1109/ICCD.1996.563563
Filename
563563
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