DocumentCode
3083331
Title
An Analytical Model for Reliability Evaluation of NoC Architectures
Author
Dalirsani, Atefe ; Hosseinabady, Mohammad ; Navabi, Zainalabedin
Author_Institution
Univ. of Tehran, Tehran
fYear
2007
fDate
8-11 July 2007
Firstpage
49
Lastpage
56
Abstract
This paper proposes an analytical model to assess Reliability Factor of an NoC based System-on-Chip design. Reliability Factor is the probability that faults in the NoC infrastructure can be recovered without any effect on system functionality. The proposed method classifies switch faults of an NoC according to their impact on system functionality. Based on this classification, the contribution of each transient fault lowering the reliability of the NoC is calculated. This model can be used to decide which fault tolerant techniques cause more improvement on system reliability.
Keywords
fault tolerance; network synthesis; network-on-chip; NoC Architectures; fault tolerant techniques; network-on-chip; reliability evaluation; switch faults; system-on-chip design; Analytical models; Circuit faults; Erbium; Error correction; Fault tolerant systems; Integrated circuit interconnections; Network-on-a-chip; Reliability; Switches; System-on-a-chip;
fLanguage
English
Publisher
ieee
Conference_Titel
On-Line Testing Symposium, 2007. IOLTS 07. 13th IEEE International
Conference_Location
Crete
Print_ISBN
0-7695-2918-6
Type
conf
DOI
10.1109/IOLTS.2007.13
Filename
4274820
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