Design and analysis of high-speed and low power Si interposer for highperformance 3D stacked systems

For IO interconnection, longer wiring induces larger signal delay and the driving power consumes proportionally the length of wiring. Therefore, high speed and low power IO design is definitely important for how to shorten wiring or to reduce power even relative longer wiring. Si interposer composed multi-chip (2.5D) provides more wiring space, however length of wiring would be longer than 3D-designed chip wiring. Thus, low-power IO system design must be required even in denser configuration. This paper is discussed from fundamental approach for reducing power of IO system.