DocumentCode :
3083457
Title :
Temporal parallel simulation: A fast gate-level HDL simulation using higher level models
Author :
Kim, Dusung ; Ciesielski, Maciej ; Shim, Kyuho ; Yang, Seiyang
Author_Institution :
Dept. of Electr. & Comput. Eng., Univ. of Massachusetts, Amherst, MA, USA
fYear :
2011
fDate :
14-18 March 2011
Firstpage :
1
Lastpage :
6
Abstract :
Simulation speedup offered by distributed parallel event-driven simulation is known to be seriously limited by the synchronization and communication overhead. These limiting factors are particularly severe in gate-level timing simulation. This paper describes a radically different approach to gate-level simulation based on a concept of temporal rather than conventional spatial parallelism. The proposed method partitions the entire simulation run into simulation slices in temporal domain and each slice is simulated separately. With each slice being independent from each other, an almost linear speedup is achievable with a large number of simulation nodes. This concept naturally enables “correct by simulation” methodology that explicitly maintains the consistency between the reference and the target specifications. Experimental results clearly show a significant simulation speed-up.
Keywords :
hardware description languages; parallel processing; simulation languages; conventional spatial parallelism; correct by simulation methodology; distributed parallel event driven simulation; fast gate level HDL simulation; gate level timing simulation; higher level model; simulation speedup; temporal parallel simulation; Clocks; Delay; Hardware design languages; Logic gates; Mathematical model; Synchronization; Event-driven simulation; Gate-level simulation; parallel simulation; verilog simulation;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Design, Automation & Test in Europe Conference & Exhibition (DATE), 2011
Conference_Location :
Grenoble
ISSN :
1530-1591
Print_ISBN :
978-1-61284-208-0
Type :
conf
DOI :
10.1109/DATE.2011.5763251
Filename :
5763251
Link To Document :
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