Title :
Modeling the difficulty of sequential automatic test pattern generation
Author :
Marchok, Thomas E. ; Maly, Wojciech
Author_Institution :
Carnegie Mellon Univ., Pittsburgh, PA, USA
Abstract :
This paper introduces a model which describes the cost of automatic test pattern generation for (non-scan) sequential logic in terms of attributes of the circuit under test. This model addresses a core issue involved in integrated circuit design and test trade-offs, and can be used to evaluate the cost effectiveness of potential design-for-testability (DFT) techniques. This knowledge can also be used to identify hard-to-test portions of designs, and therefore to devise more cost-effective DFT techniques
Keywords :
VLSI; automatic testing; design for testability; integrated circuit design; integrated circuit testing; logic CAD; logic testing; sequential circuits; VLSI; circuit attributes; cost effectiveness; design-for-testability; integrated circuit design; integrated circuit test; logic CAD; modeling; sequential automatic test pattern generation; sequential logic; Automatic logic units; Automatic test pattern generation; Automatic testing; Circuit testing; Costs; Design for testability; Integrated circuit modeling; Logic testing; Sequential analysis; Sequential circuits;
Conference_Titel :
Computer Design: VLSI in Computers and Processors, 1996. ICCD '96. Proceedings., 1996 IEEE International Conference on
Conference_Location :
Austin, TX
Print_ISBN :
0-8186-7554-3
DOI :
10.1109/ICCD.1996.563566
