DocumentCode
3083882
Title
Background digital error correction technique for pipelined analog-digital converters
Author
Sonkusale, Sameer R. ; Van der Spiegel, Jan ; Nagaraj, K.
Author_Institution
Dept. of Electr. Eng., Pennsylvania Univ., Philadelphia, PA, USA
Volume
1
fYear
2001
fDate
6-9 May 2001
Firstpage
408
Abstract
This paper describes a technique for digital error correction in pipelined analog-digital converters. It makes use of a slow, high resolution ADC in conjunction with an LMS algorithm to perform error correction in the background during normal conversion. The algorithm has been shown to correct for errors due to capacitor ratio mismatch, finite amplifier gain and charge injection within the same framework
Keywords
analogue-digital conversion; error correction; least mean squares methods; pipeline processing; LMS algorithm; background digital error correction technique; capacitor ratio mismatch; charge injection; finite amplifier gain; high resolution ADC; pipelined ADC; pipelined analog-digital converters; Analog-digital conversion; Calibration; Capacitors; Dynamic range; Error correction; Instruments; Least squares approximation; Operational amplifiers; Pipelines; Voltage;
fLanguage
English
Publisher
ieee
Conference_Titel
Circuits and Systems, 2001. ISCAS 2001. The 2001 IEEE International Symposium on
Conference_Location
Sydney, NSW
Print_ISBN
0-7803-6685-9
Type
conf
DOI
10.1109/ISCAS.2001.921879
Filename
921879
Link To Document