Author :
Gericota, Manuel G. ; Lemos, Luís F. ; Alves, Gustavo R. ; Ferreira, José M.
Abstract :
To boost logic density and reduce per unit power consumption SRAM-based FPGAs manufacturers adopted nanometric technologies. However, this technology is highly vulnerable to radiation-induced faults, which affect values stored in memory cells, and to manufacturing imperfections. Fault tolerant implementations, based on Triple Modular Redundancy (TMR) infrastructures, help to keep the correct operation of the circuit. However, TMR is not sufficient to guarantee the safe operation of a circuit. Other issues like module placement, the effects of multi- bit upsets (MBU) or fault accumulation, have also to be addressed. In case of a fault occurrence the correct operation of the affected module must be restored and/or the current state of the circuit coherently re-established. A solution that enables the autonomous restoration of the functional definition of the affected module, avoiding fault accumulation, re-establishing the correct circuit state in real-time, while keeping the normal operation of the circuit, is presented in this paper.
Keywords :
SRAM chips; fault tolerance; field programmable gate arrays; nanotechnology; SRAM-based FPGA manufacturers; fault accumulation; fault tolerant implementations; logic density; multibit upsets; nanometric technologies; on-line self-healing; real-time; reconfigurable FPGA; triple modular redundancy infrastructures; Circuit faults; Clocks; Computer aided manufacturing; Electromigration; Fault detection; Field programmable gate arrays; Flip-flops; Power engineering computing; Redundancy; Single event upset;