DocumentCode
3083985
Title
Design of a 14 b 100 MS/s switched-capacitor pipelined ADC in RFSiGe BiCMOS
Author
Bugeja, Alex R. ; Kwak, Sung-Ung
Author_Institution
Texas Instrum. Inc., Dallas, TX, USA
Volume
1
fYear
2001
fDate
6-9 May 2001
Firstpage
428
Abstract
This work presents some important design considerations for a 14 b 100 MS/s switched capacitor pipelined ADC designed in TI´s proprietary RFSiGe BiCMOS process. Simulation results for key blocks including the track/hold and MDAC operational amplifier are given, and an analysis of the clock jitter in the clocking circuitry is presented to justify its design
Keywords
BiCMOS integrated circuits; Ge-Si alloys; analogue-digital conversion; integrated circuit design; operational amplifiers; pipeline processing; radio receivers; sample and hold circuits; switched capacitor networks; timing jitter; ADC design; MDAC operational amplifier; RF SiGe BiCMOS; SiGe; clock jitter; digital receiver; linearity; settling characteristic; simulation; switched-capacitor pipelined ADC; track/hold circuit; BiCMOS integrated circuits; Capacitors; Circuit noise; Clocks; Instruments; Linearity; MOS devices; Noise cancellation; Operational amplifiers; Pipelines;
fLanguage
English
Publisher
ieee
Conference_Titel
Circuits and Systems, 2001. ISCAS 2001. The 2001 IEEE International Symposium on
Conference_Location
Sydney, NSW
Print_ISBN
0-7803-6685-9
Type
conf
DOI
10.1109/ISCAS.2001.921884
Filename
921884
Link To Document