A 1-V, 10-bit rail-to-rail successive approximation analog-to-digital converter in standard 0.18 μm CMOS technology

Author

Fayomi, Christian Jesus B ; Roberts, Gordon W. ; Sawan, Molianiad

Author_Institution

Dept. of Electr. & Comput. Eng., Ecole Polytech., Montreal, Que., Canada

Volume

1

fYear

2001

fDate

6-9 May 2001

Firstpage

460

Abstract

Two architectures for a 1-V, 10-bit 200-kS/s successive approximation analog-to-digital converter (ADC) implemented in a standard CMOS 0.18 μm digital process are presented. A track-and-hold circuit based on a novel implementation of the bootstrapped low-voltage analog CMOS switch with a novel rail-to-rail track-and-latch comparator circuit is described. A pMOS-only ladder containing a rail-to-rail current-to-voltage converter, performs the DAC function in the second ADC topology whereas a conventional R-2R ladder is used in the first one. Successive approximation and control logic is implemented using of robust single clock phase D flip flop

Keywords

CMOS integrated circuits; SPICE; analogue-digital conversion; comparators (circuits); low-power electronics; mixed analogue-digital integrated circuits; sample and hold circuits; 0.18 micron; 1 V; DAC function; HSPICE; bootstrapped low-voltage analog CMOS switch; control logic; conventional R-2R ladder; mixed signal system; pMOS-only ladder; rail-to-rail current-voltage converter; rail-to-rail successive approximation ADC; robust single clock phase D flip flop; standard CMOS technology; track-and-hold circuit; track-and-latch comparator circuit; Analog-digital conversion; CMOS process; CMOS technology; Circuits; Dynamic range; Laboratories; Microelectronics; Power supplies; Threshold voltage; Wide area networks;

fLanguage

English

Publisher

ieee

Conference_Titel

Circuits and Systems, 2001. ISCAS 2001. The 2001 IEEE International Symposium on

Conference_Location

Sydney, NSW

Print_ISBN

0-7803-6685-9

Type

conf

DOI

10.1109/ISCAS.2001.921892

Filename

921892