The direct-mapped instruction cache for ColdFire microprocessors

This paper describes the design considerations and main features of the ColdFire direct-mapped instruction cache. This cache is also available via Motorola´s FlexCore program, in sizes of 0.5-32 K. The cache utilizes “compiled” memory arrays for directory (tag) and instruction data storages. The cache incorporates a 16-byte fill-buffer that enables non-lockup (hit-under-miss) operation. The fill-buffer also functions as a “floating” second-set to improve cache hit rate. Included in this paper are a description of a low-cost method of reducing conflict misses and the introduction of the notion of a miss-fetch algorithm to maximize cache performance and simultaneously minimize external bus-utilization