• DocumentCode
    3084326
  • Title

    The effect of supply voltage reduction to 5.8-GHz differential dual-modulus prescaler

  • Author

    Mitsunaka, Takeshi ; Yamanoue, Masafumi ; Iizuka, Kunihiko ; Fujishima, Minoru

  • Author_Institution
    SHARP Corp., Hiroshima, Japan
  • fYear
    2013
  • fDate
    5-6 June 2013
  • Firstpage
    30
  • Lastpage
    31
  • Abstract
    We have measured the noise floor of spectrum and phase noise of the proposed differential dual-modulus 10/11 prescaler based on ILFD for various supply voltages and found that spurious noises arise and the phase noise degrades as the supply voltage reduces. The differential dual-modulus prescaler is implemented in 130 nm CMOS process and the core size is 40 × 20 μm2.
  • Keywords
    CMOS integrated circuits; frequency dividers; prescalers; CMOS process; ILFD; differential dual-modulus 10/11 prescaler; frequency -5.8 GHz; injection locked frequency dividers; noise floor; phase noise; size 130 nm; supply voltage reduction; ILFD; Phase Noise; Prescaler; Quasi-Locking;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Future of Electron Devices, Kansai (IMFEDK), 2013 IEEE International Meeting for
  • Conference_Location
    Suita
  • Print_ISBN
    978-1-4673-6106-4
  • Type

    conf

  • DOI
    10.1109/IMFEDK.2013.6602226
  • Filename
    6602226
    • Link To Document
    https://search.isc.ac/dl/search/defaultta.aspx?DTC=49&DC=3084326