DocumentCode
3084649
Title
A 450 MHz IA32 P6 family microprocessor
Author
Schutz, J. ; Wallace, R.
Author_Institution
Intel Corp., Hillsboro, OR, USA
fYear
1998
fDate
5-7 Feb. 1998
Firstpage
236
Lastpage
237
Abstract
A 1.4 V to 2.2 V 450 MHz CMOS 1.5 M transistor microprocessor in 131 mm/sup 2/ makes use of a five-layer-metal 0.25 /spl mu/m process technology. This is the third generation implementation of this microprocessor. This microprocessor implements the full Intel instruction set, including MMX(TM) technology instruction set extensions. This implementation adds new support for back side bus caches that transfer data at the core clock rate in 1 MB and 2 MB implementations to support 4-way servers.
Keywords
microprocessor chips; 0.25 micron; 1 to 2 MB; 1.4 to 2.2 V; 450 MHz; CMOS; IA32 P6 family microprocessor; Intel instruction set; MMX technology; back side bus caches; core clock rate; five-layer-metal process technology; four-way servers; instruction set extensions; Bonding; Capacitance; Clocks; Coupling circuits; Jitter; Microprocessors; Packaging; Silicon; Space technology; Wire;
fLanguage
English
Publisher
ieee
Conference_Titel
Solid-State Circuits Conference, 1998. Digest of Technical Papers. 1998 IEEE International
Conference_Location
San Francisco, CA, USA
ISSN
0193-6530
Print_ISBN
0-7803-4344-1
Type
conf
DOI
10.1109/ISSCC.1998.672450
Filename
672450
Link To Document