A 10-bit, 2.5-V, 40 M sample/s, pipelined analog-to-digital converter in 0.6-μm CMOS

Author

Nejati, Babak ; Shoaei, Omid

Author_Institution

Dept. of Electr. & Comput. Eng., Tehran Univ., Iran

Volume

1

fYear

2001

fDate

6-9 May 2001

Firstpage

576

Abstract

A high-speed, low-voltage pipelined analog-to-digital converter is presented. It achieves 58 dB SNDR with full-scale Nyquist rate sinusoidal input and conversion rate of 40 MHz with a power supply of 2.25 V. A 1.5 bit per stage architecture is used for all the stages except the first one. The first stage employs more comparators to reduce the signal swing at the output of the stage, hence relaxes conditions on the op-amp transistor sizes in the subsequent stages. Simulation results have been checked with all process corners from -40°C to +120°C and ±15% variation in poly-poly capacitor sizes

Keywords

CMOS integrated circuits; analogue-digital conversion; high-speed integrated circuits; pipeline processing; -40 to 120 C; 10 bit; 2.25 V; 2.5 V; 40 MHz; CMOS ADC; analog-to-digital converter; comparators; high-speed ADC; pipelined ADC; poly-poly capacitors; Analog-digital conversion; CMOS process; Capacitors; Digital signal processing; Operational amplifiers; Pipelines; Power dissipation; Power supplies; Sampling methods; Transfer functions;

fLanguage

English

Publisher

ieee

Conference_Titel

Circuits and Systems, 2001. ISCAS 2001. The 2001 IEEE International Symposium on

Conference_Location

Sydney, NSW

Print_ISBN

0-7803-6685-9

Type

conf

DOI

10.1109/ISCAS.2001.921921

Filename

921921