A low power 10 bit, 80 MS/s CMOS pipelined ADC at 1.8 V power supply

Author

Park, Yong-In ; Karthikeyan, S. ; Tsay, Frank ; Bartolome, E.

Author_Institution

Data Converter Group, Texas Instrum. Inc., Dallas, TX, USA

Volume

1

fYear

2001

fDate

6-9 May 2001

Firstpage

580

Abstract

CMOS process technology has been moving rapidly towards finer geometry for higher system integration faster clock frequencies and lower power consumption. With deep sub-micron CMOS transistors, the voltage supply has been reduced from 5.0 V to 3.3 V and even to 1.8 V. Lower supply voltage presents a major challenge to analog circuit design due to mostly reduced dynamic range and lower SNR and SINAD. While 1.5 V ADC has been designed at 10-bit resolution, the performance has been limited to less than 20 Msps. Other 10-bit, 100 MS/s ADCs have been demonstrated, yet with higher supply voltage and higher power consumptions. This paper introduces a design that addresses the issues of 1.8 V supply in a 10-bit 80 MS/s pipeline ADC implemented in a 0.18 μm CMOS process. The total power consumption of the chip is only 80 mW, which is the least compared to other ADCs with similar performance reported in the literature to date

Keywords

CMOS integrated circuits; analogue-digital conversion; high-speed integrated circuits; low-power electronics; pipeline processing; 0.18 micron; 1.8 V; 10 bit; 80 mW; CMOS pipelined ADC; CMOS process technology; deep submicron CMOS; low power ADC; Analog circuits; CMOS analog integrated circuits; CMOS process; CMOS technology; Clocks; Dynamic range; Energy consumption; Frequency; Geometry; Voltage;

fLanguage

English

Publisher

ieee

Conference_Titel

Circuits and Systems, 2001. ISCAS 2001. The 2001 IEEE International Symposium on

Conference_Location

Sydney, NSW

Print_ISBN

0-7803-6685-9

Type

conf

DOI

10.1109/ISCAS.2001.921922

Filename

921922