DocumentCode :
3084723
Title :
A sub-10nm U-shape FinFET design with suppressed leakage current and DIBL effect
Author :
Wei-Chao Zhou ; Peng-Fei Wang ; Zhang, David Wei
Author_Institution :
State Key Lab. of ASIC & Syst., Fudan Univ., Shanghai, China
fYear :
2015
fDate :
15-16 March 2015
Firstpage :
1
Lastpage :
3
Abstract :
In this paper, a U-shape fin field-effect transistor (U-FinFET) is proposed for sub-10nm technology and low power applications. Compared with the conventional tri-gate fin field-effect transistor (FinFET), this structure has the advantages of relatively low off-state channel leakage current (Ioff) and sub-threshold swing (SS). By using Sentaurus TCAD simulations, it is found that the U-shape channel can also suppress the drain induced barrier lowering (DIBL) effect.
Keywords :
MOSFET; leakage currents; technology CAD (electronics); DIBL effect; Sentaurus TCAD simulation; U-FinFET design; U-shape fin field-effect transistor; drain induced barrier lowering effect; leakage current suppression; low power application; off-state channel leakage current; subthreshold swing; Doping; FinFETs; Junctions; Leakage currents; Logic gates; Threshold voltage;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Semiconductor Technology International Conference (CSTIC), 2015 China
Conference_Location :
Shanghai
ISSN :
2158-2297
Type :
conf
DOI :
10.1109/CSTIC.2015.7153322
Filename :
7153322
Link To Document :
https://search.ricest.ac.ir/dl/search/defaultta.aspx?DTC=49&DC=3084723
بازگشت