A 200 MHz 32 b 0.5 W CMOS RISC microprocessor

Author

Stephany, R. ; Anne, K. ; Bell, Jonathan ; Cheney, G. ; Eno, J. ; Hoeppner, G. ; Joe, G. ; Kaye, R. ; Lear, J. ; Litch, T. ; Meyer, Jorg ; Montanaro, J. ; Patton, K. ; Pham, Thach ; Reis, R. ; Silla, M. ; Slaton, J. ; Snyder, K. ; Witek, R.

Author_Institution

Digital Semicond., Austin, TX, USA

fYear

1998

fDate

5-7 Feb. 1998

Firstpage

238

Lastpage

239

Abstract

This custom RISC microprocessor delivers approximately 230 Drystone/MIPS at 200 MHz while dissipating 0.5 W from a 1.5 V internal supply. The internal supply can be biased from 1.5 V to 2.0 V, while the external supply is always biased at 3.3 V. A split supply minimizes power consumption for a given application, while maintaining compatibility with a 3.3 V external environment. The die contains 2.5 M transistors and is 8.24/spl times/9.12 mm/sup 2/. It is fabricated in a 0.35 /spl mu/m, 2.0 V, n-well, single-poly, 3-metal-layer CMOS process. It is packaged in a 208 pin thin quad flat pack.

Keywords

CMOS digital integrated circuits; 0.35 micron; 0.5 W; 1.5 to 2.0 V; 200 MHz; 3.3 V; 32 bit; CMOS; RISC microprocessor; compatibility; external supply; internal supply; n-well single-poly 3-metal-layer process; power consumption; thin quad flat pack; Circuits; Clocks; Energy consumption; Energy management; Frequency; Latches; Microprocessors; Oscillators; Reduced instruction set computing; Wire;

fLanguage

English

Publisher

ieee

Conference_Titel

Solid-State Circuits Conference, 1998. Digest of Technical Papers. 1998 IEEE International

Conference_Location

San Francisco, CA, USA

ISSN

0193-6530

Print_ISBN

0-7803-4344-1

Type

conf

DOI

10.1109/ISSCC.1998.672451

Filename

672451