System-level modeling of a mixed-signal System on Chip for Wireless Sensor Networks

Due to the increasing advance on wireless communication and sensors, Wireless Sensor Networks (WSN) have been widely used in several fields, such as medicine, science, industrial automation and security. A possible solution is to use CMOS System on Chip (SoC) sensor nodes as hardware platforms due to its extremely low power, sensing, computation and communication capabilities. This work presents the modeling of a mixed-signal SoC for WSN using a system-level approach. The digital section was modeled using SystemC Transaction Level Modeling (TLM) and consists of a 32-bit RISC microprocessor, memory, interrupt controller and serial interface. The analog block consists of an Analog-to-Digital Converter (ADC) described in SystemC-AMS. An application was implemented to test the correctness of the model and perform the communication between the SoC and a functional level node model.