Interconnect metrology roadmap: status and future

Author

Diebold, Alain C. ; Goodall, Randal K.

Author_Institution

Sematech, Austin, TX, USA

fYear

1999

fDate

1999

Firstpage

77

Lastpage

79

Abstract

All areas of metrology are challenged by the reduced feature size associated with the introduction of new technology generations. Metrology for the processes used to fabricate on-chip interconnects will be even more difficult due to new materials and processes. In this paper, we assume that copper metallization and damascene processing will become the interconnect technology of choice. Metrology developments and requirements for metal and dielectric films, critical dimensions for interconnect structures, chemical mechanical polishing, and defect detection are covered

Keywords

chemical mechanical polishing; copper; dielectric thin films; fault location; integrated circuit interconnections; integrated circuit measurement; integrated circuit metallisation; integrated circuit reliability; Cu; chemical mechanical polishing; copper metallization; critical dimensions; damascene processing; defect detection; dielectric films; feature size; interconnect materials; interconnect metrology roadmap; interconnect processes; interconnect structures; interconnect technology; metal films; metrology; on-chip interconnects; technology generations; Acoustic measurements; Conductivity; Copper; Dielectric constant; Dielectric materials; Dielectric measurements; Metrology; Optical films; Process control; Thickness measurement;

fLanguage

English

Publisher

ieee

Conference_Titel

Interconnect Technology, 1999. IEEE International Conference

Conference_Location

San Francisco, CA

Print_ISBN

0-7803-5174-6

Type

conf

DOI

10.1109/IITC.1999.787083

Filename

787083